A GaN half bridge wants roughly half the dead time of silicon, and in EPC's measurement every 10 ns of total dead time per cycle cost about one point of efficiency. In a three phase GaN inverter the guard interval between one switch turning off and the other turning on decides more of the efficiency than almost anything else you tune in firmware. For a fast GaN half bridge the right value lives in the single digit to low tens of nanoseconds, and the primary source below is EPC's white paper WP012 on dead time optimisation [1].
Why the window is narrow
Set dead time too short and both switches conduct at once, which is shoot through. Set it too long and current is forced through the device in reverse for longer than needed. A GaN FET has no body diode; its reverse conduction is the channel conducting backwards, a majority carrier process with no reverse recovery charge [1]. The price is a higher forward drop: EPC shows the eGaN FET reverse voltage about 1.5 V above a silicon body diode at 25 °C, widening toward 2 V as temperature rises [1]. So each nanosecond of reverse conduction costs more in GaN, but there is no recovery charge to sweep out when it ends.
EPC calculates the losses for a 60 V bus with 100 V eGaN FETs against similar on resistance 80 V MOSFETs: self commutation times are about half as long thanks to lower output capacitance, and hard commutation plus reverse recovery loss is about a third, 36 percent, of the MOSFET figure [1]. The net result is that the optimum dead time range for GaN is about 50 percent of the MOSFET range [1].
The numbers, with their conditions attached
Our first draft mislabelled these ranges, so here they are with the conditions EPC states. These are calculated effective dead times, threshold to threshold, not measurements. Across a 4 A to 20 A load sweep, the dynamic optimum on a 60 V bus is 5 ns to 20 ns for the eGaN FET against 9 ns to 36 ns for the MOSFET [1]. For a design that must use one fixed dead time at every load, EPC gives 20 ns ± 7 ns and 44 ns ± 16 ns respectively, both holding dead time loss under 1 µJ per event [1]. On a 12 V bus with 40 V eGaN FETs against 30 V MOSFETs, the dynamic optimum shrinks to 3 ns to 6 ns against 7 ns to 13 ns, and the fixed dead time windows are less than 6 ns wide, which EPC says may be difficult to generate with the required accuracy [1].
The 60 V row is the one that maps onto a 48 V joint drive. Read it as a target of 5 ns to 20 ns depending on load, or a fixed setting near 20 ns if the timing generator cannot follow the current. Two other data points bracket it: EPC's own EPC2152 BLDC inverter runs 10 ns per edge where it says MOSFET stages start at 50 ns [3], and TI puts GaN dead time at 10 ns to 20 ns against about 1 µs for the silicon MOSFET stages it compares in a humanoid joint drive [2].
What it costs when you get it wrong
The measured relationship is blunt. In a 40 V eGaN buck converter running at 1 MHz from 12 V to 1.2 V, every 5 ns of effective dead time per edge, 10 ns total per cycle, cost about 1 percent of efficiency, roughly twice the sensitivity of the MOSFET converter tested alongside it [1]. That is a low voltage, high frequency point, and the loss per nanosecond scales down at lower frequency, but the mechanism is the same one a 48 V, 100 kHz joint drive carries.
EPC then added a small, deliberately undersized 1 A Schottky diode in parallel with the eGaN FET. Dead time loss fell by as much as 70 percent around 10 A load and by more than 50 percent across the sweep, with the improvement shrinking at higher current as the diode's forward drop rises [1]. A larger diode would move the peak improvement to higher current [1].
Why does an external diode work with GaN when it does not with silicon? EPC's answer is threefold: no body diode reverse recovery, so partial commutation to the Schottky still helps; the higher GaN reverse drop actually speeds current commutation into the diode; and the low inductance LGA package keeps the commutation loop short enough to matter [1]. The diode has to sit next to the FET on the same side of the board in a low inductance package, or the advantage disappears [1].
The takeaway for a joint drive
For a 48 V to 60 V actuator drive switching hard and fast, dead time is not a detail you set once. It is a first class efficiency lever, and in our reading the right implementation is dynamic: track the load current and shorten the guard band as the current rises, exactly the direction EPC's optimum ranges point. A fixed 20 ns is a defensible compromise; a fixed 50 ns inherited from a silicon design is not. The open question is how much of the remaining loss a well placed Schottky recovers at 48 V and 30 A, where nobody has published the sweep.
References
- J. Strydom and D. Reusch, Dead-Time Optimization for Maximum Efficiency, EPC white paper WP012, Efficient Power Conversion Corporation.
- Texas Instruments, Application of GaN FET in Humanoid Robots, SNOAAB3, January 2025.
- EPC, How2AppNote 017: How to Design a Compact Low-voltage BLDC Motor Drive Inverter Using a Monolithic GaN ePower Stage, rev. 23 June 2021.