A monolithic GaN power stage makes a compact three phase inverter possible, and the same switching speed that buys the efficiency is what makes the layout unforgiving. EPC's How2AppNote017 builds a 60 V BLDC inverter around the EPC2152, a half bridge with two 70 V, 10 mΩ FETs and their gate driver in one 3.9 mm by 2.6 mm package that carries up to 15 A and switches up to 3 MHz [1]. The board measures 45 mm by 55 mm and is designed for 15 V to 60 V input, 20 kHz to 1 MHz, and a 400 W NEMA 34 motor [1]. This is the design note version of a lesson we also learned on our own board [3].
The device sets the pace
Monolithic integration is not only about size. EPC attributes it to three things at once: lower common source inductance, lower power and gate loop inductance, and a more even spread of dissipation inside the IC [1]. Component count drops and the layout gets simpler, on paper.
Run from 48 V at 100 kHz into the 400 W motor at 10 A rms per phase, the switch node transitions in one to two nanoseconds. With current flowing out of the node the rise is 1 ns and the fall 1.7 ns; with current flowing in, the rise is 1.9 ns and the fall 1.2 ns [1]. Our first draft quoted only the fastest edge of each pair, which was flattering and wrong. The honest statement is that every edge is under 2 ns.
The dead times of the half bridges were set to 10 ns on both edges, which EPC describes as very short against MOSFETs that start at 50 ns [1]. Without a dynamometer, EPC measured inverter loss at no load against phase current and extrapolated to 400 W: efficiency, including 184 mW for the controller, exceeds 98.4 percent [1]. Without a heatsink and with 400 LFM of forced air at 9 A rms, the three power stages sat at 52.0, 54.9 and 52.7 °C [1].
The catch is the loop, not the chip
A 1 ns edge across even a small parasitic inductance is a large voltage. In our experience that is where compact GaN inverters fail. On our own ulna bring up, every half bridge failure landed in a single phase, the middle leg, and our reading is that its power loop carried more parasitic inductance than the two outer legs [3]. The device was fine. The copper was not.
EPC's own note says the same thing in the positive: each phase uses one EPC2152 with only a few support capacitors [1], and EPC's stated reason the monolithic stage switches cleanly is the reduction in common source, power loop and gate loop inductance that integration brings [1]. What the package does not do is protect you from the loop you draw around it. The rules we now apply are ours, not EPC's: keep the power loop area as small as the footprint allows, put the input capacitance directly at each half bridge, give every leg the same low impedance path, and treat the middle phase with the same care as the outer two rather than with whatever space is left.
Then the heat
Low switching loss is what lets the package stay small, but the thermal path still sets the limit. The relevant number here comes from a different device and a different vendor, so it is a comparison of principle rather than of parts. Innoscience bonded a 70 mm by 35 mm by 25 mm heatsink to the underside of its three phase ISG3204LA demo board through a 4 W/mK thermal interface and measured the device case roughly 30 °C cooler than the bare board at 48 V, 20 kHz, 100 ns dead time and 20 A rms [2]. On the EPC board the same job is done by 400 LFM of air and threaded posts for an optional heatsink [1].
Compact and cool are not in tension for GaN, provided the loop is tight and the heat has somewhere to go. The open question for a joint drive is which of the two you run out of first: the last millimetre of loop, or the last square centimetre of heatsink.
References
- EPC, How2AppNote 017: How to Design a Compact Low-voltage BLDC Motor Drive Inverter Using a Monolithic GaN ePower Stage, rev. 23 June 2021.
- Innoscience, DB043 INNDMD48V22A1 48 V 22 A Motor Drive Featuring ISG3204LA Demo Manual, rev. 1.0, Chinese edition.
- Aleph-B, ulna-60-30 BLDC controller test report, v1.0, 22 June 2026, internal.