On a circular joint PCB, three single half bridge gate drivers beat one three phase driver, and the reason is trace length rather than silicon. Every claimed benefit of the split approach traces back to the same physical fact: a driver sitting beside its own FET pair has a gate loop measured in millimetres, while a central driver feeding three FET pairs around a ring has three long, unequal gate and source paths.
That is a layout argument. It is also the strongest argument, because gate loop inductance is the parameter that sets your ringing, your EMI floor, and how hard you are allowed to switch.
The geometry problem nobody designs around
A joint actuator gives you a ring PCB, typically 5 cm to 10 cm in diameter, and in our experience a hole in the middle for the shaft [4]. Power devices go near the edge where the copper and the thermal path are. A single three phase driver has to live somewhere, and wherever you put it, at least two phases are far away.
Split the driver into three and the geometry stops fighting you. Each driver sits beside its half bridge. Gate and source traces shorten, trace inductance drops, ringing and overshoot drop with it, and so does the radiated noise the rest of the robot has to tolerate [1][2].
The scaling argument is separate and also real. Robotics spans power levels from 10 W to 4 kW and above, typically on a 48 V rail, covering payloads from 2 kg to 40 kg [1]. A single half bridge building block lets one driver family serve a finger actuator and a hip actuator without redesigning the gate drive twice.
Gate current granularity replaces the gate resistor
Here is the part that changes your BOM. TI's DRV8162 exposes 16 gate drive current settings, where TI describes competing half bridge drivers as offering a fixed current or two to four discrete settings, with source current from 16 mA to 1024 mA and sink from 32 mA to 2048 mA [1].
With coarse settings you hit your target slew rate by adding external gate resistors. With 16 settings plus a programmable sink to source ratio, you set slew rate in firmware and delete the passives. On a board where every square millimetre near the FET is contested, that is not a rounding error.
The selection method is straightforward arithmetic. Drive current follows from the device gate to drain charge and the transition time you want [1]:
I_DRIVE (A) = Q_gd (nC) / t_rise or t_fall (ns)
Work TI's case. Target 1 V/ns on a 48 V rail and you are asking for a 48 ns transition [1]. Run that against the driver's current range and the device covers gate charges from 0.77 nC to 49.15 nC on the source side, and 1.54 nC to 98.30 nC on the sink side [1]. That window, not the current range itself, is the portability metric: it tells you which FETs one driver can carry across your product line.
Note that sink sits at exactly twice source at both ends of the range. TI states only that the ratio is programmable. Our reading of why a designer wants the asymmetry: the low side gate needs a stronger pull down to stay off against dV/dt induced Miller turn on when the opposite switch commutates, and at GaN edge rates that is not a theoretical concern.
Dead time as a product specification
The DRV8162 runs with a 20 ns dead time, and TI ties that to better efficiency, a wider usable PWM duty cycle range, less current distortion and less audible noise [1].
The acoustic one deserves attention because it is a product level property expressed in nanoseconds. Dead time distortion produces harmonic content in the phase current, and harmonic content in the phase current is what makes a robot whine. A humanoid working beside people is judged on that. A gate driver timing parameter is not usually where you would look for it.
The duty cycle consequence is more quantitative. Dead time subtracts from usable duty cycle on every switching period. At 20 ns against the 12.5 µs period of an 80 kHz GaN stage [4] you lose almost nothing. At the roughly 1 µs that silicon MOSFET stages need [4], two edges on that same 12.5 µs period take 16 percent of the available motor voltage, our arithmetic, which is 16 percent of your top speed.
Where safe torque off lands
The architectural decision worth noting: the DRV8162 and DRV8162L carry a split supply architecture intended to help implement safe torque off [1]. The mechanism, described in TI's STO application brief, is to disconnect the gate driver power supply so the power switches turn off because their drivers no longer have a rail to drive from [3]. Our reading of TI's Figure 1 is that this path is independent of the PWM path and the processor. IEC 61800-5-2 defines the function as preventing force producing power from being provided to the motor [3].
TI proposes this STO concept on a 48 V, 4 kW three phase inverter reference design, TIDA-010956, rated for 85 Arms output and built on the DRV8162L with parallel FETs [1].
The question a design team should ask before adopting it: a supply removal safe state relies on gate charge decaying and on the switches staying off while it does. That behaviour under dV/dt at 48 V or 60 V is worth characterising on your own board rather than assuming.
The trade being made
Three drivers instead of one costs parts. TI's own comparison counts one capacitor or resistor per configuration pin for the three phase driver against three for the split version, across eight pins: GVDD, VDRAIN, CSAREF, IDRIVE, VDS level, dead time, CSA gain and nFault [2]. You are spending parts count to buy gate loop quality and architectural reuse.
For a discrete power stage on a constrained ring PCB, that trade looks correct. For a design built on GaN devices with the driver already integrated in the package, much of the same benefit arrives for free, and the interesting comparison shifts to integrated GaN half bridges against discrete FET plus separate driver. That is the comparison we run on every ulna revision.
References
- Texas Instruments, Cobots to Humanoids: Driving System Efficiency and Safety into Higher-Power Robots, SSZTD67, November 2024.
- Texas Instruments, Three-Phase vs Three-Single Half-Bridge Gate Drivers, SLVAFZ0, November 2024.
- Texas Instruments, Design Smaller Safe Torque Off (STO) Systems Using Integrated 3-Phase Smart Gate Drivers, SLVAF31, March 2021.
- Texas Instruments, Application of GaN FET in Humanoid Robots, SNOAAB3, January 2025.