The first ulna-60-30 boards on the bench: a wrong regulator, a layout that only phase V could expose, and the buses that came up clean. This is the log from powering our first ulna-60-30 controllers. We write these up in full because the useful part of building hardware is not the plan, it is what the board actually does the first time it sees voltage. Every number below comes from our own test report [1].
Power on, and the first surprise
Visual inspection and a multimeter short check on the supply line and between the motor phases both came back clean [1]. First power on used a lab supply at 12 V with the current limit set to 0.2 A. The board drew 80 mA and the green LED1 lit. The 5 V rail measured 5.1 V, correct. The nominal 3.3 V rail measured 4.2 V, which is not [1].
Root cause was the switching regulator U10, a TPS613221ADBVT, selected incorrectly for that rail. To keep testing moving we swapped it for an AMS1117-3.3 LDO. The rail came back to 3.3 V and the input current dropped to 40 mA [1]. Under steady state the LDO was the hottest part on the board at 35 °C, which is expected for a linear regulator carrying that drop and is well inside margin [1].
Bringing up the microcontroller and the buses
The STM32 came up over SWD with an ST-LINK and STM32CubeIDE with no issues [1]. Basic firmware generated a 1 kHz square wave at 50 percent duty on pin PB4 using Timer 3, with the core clock configured to 160 MHz [1]. CAN FD on the TCAN3414 ran a request and response loop at 1 Mbps: 10,000 frames sent, 10,000 received, zero errors [1]. RS-485 on the THVD1450 ran clean at 115200 bps across roughly 3,000 frames over ten minutes [1]. We later pulled the RS-485 transceiver entirely because it could not keep up with the near 2 Mbps we wanted for field oriented control debugging, and we now recommend a dedicated high speed UART debug port on the next revision [1].
The failure that taught us the most
During motor testing we lost several half bridges. The striking part is the distribution: every failure was in phase V, the middle half bridge on the board [1]. The device was not the problem. The layout was. Fast GaN transitions across parasitic inductance in that leg produced voltage overshoot large enough to kill the switch. The fix is a power loop with very low parasitic inductance and a low impedance supply right at each half bridge [1].
The design note version of this lesson is in our companion article on compact GaN inverter layout [2], built on EPC's switch node measurements of a monolithic GaN stage, where every edge is under 2 ns [3].
Open items
Sensorless field oriented control ran stably and held speed under a light hand load [1]. Feedback from the MA732 magnetic encoder was less stable, and we saw a real mismatch between the encoder angle and the estimator angle. The cause is still open and unlikely to be simple magnet misalignment. Stability improved as speed rose [1]. We also moved the current sense amplifiers to bidirectional INA241 parts [1]. These are the honest edges of the bring up, and we would rather publish them than pretend the first board was perfect.
References
- Aleph-B, ulna-60-30 BLDC controller test report, v1.0, updated 22 June 2026, internal: test phases A1 through E1, general remarks and additional modifications.
- Aleph-B notebook, A Monolithic GaN Stage Switches in a Nanosecond, and the Layout Has No Slack, 21 September 2026.
- EPC, How2AppNote 017: How to Design a Compact Low-voltage BLDC Motor Drive Inverter Using a Monolithic GaN ePower Stage, rev. 23 June 2021, Figure 7.